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Nischay Varma Mudida - Richardson, TX, USA
Dear Hiring Manager, I am currently an EE student pursuing my Masters at The University of Texas at Dallas, Texas. I am currently seeking an internship for Spring and Summer 2013 ...
Skills: matlab, awr microwave office, awr vss, awr axiem, model sim hspice, cosmoscope, cadence
Regional Manager - Australia & New Zealand with 8 years experience in Engineering / Technical Services industry. Objective: I have strong Engineering plus Industrial Marketing & Management background ...
Skills: designcad, sap, pspice, hspice & cadance - circuit design tools, ms office
Project Manager with 10 years experience in Project industry. Responsilbilities: Feb, 1999 to date advanced engineering research organization (pvt) ltd, wah cantt, pakistan. / manager r&d / ...
Skills: ms project, primavera 5.0, project management
Mayuresh Bhosale - San Diego, CA, USA
Skills: quality education in my undergraduate and graduate institut
Mohammed Iqbal Gudmal - Richardson, TX, USA
I am fresh graduate MS 2010 in Electrical Engineering from Univ of Texas at Dallas. I am looking forward to jobs in Digital, ASIC design and verification.
Skills: c, verilog, vhdl, virtuoso, spectre, icfb, hspice, synopsys,
SONAL MITTAL - Raleigh, NC, USA
I, Sonal Mittal, have graduated from North Carolina State University, with a Master’s degree in Computer Engineering. My area of specialization is Programming, Circuit Design and Verification.
Skills: c, c, verilog, system verilog, modelsim, questasim, hspice, cadence, synopsys
Harwinder Singh - Fremont, CA, USA
I recently completed M.S. in Embedded Electrical and Computer Systems from San Francisco State University. My major interest is chip designing and reliability issues.
Skills: c++, verilog, vhdl, hspice, matlab, perl, synopsys cosmos tools, synopsys vcs tools
Gaurav Gupte - Los Angeles, CA, USA
I am interested in full time positions in ASIC Design and Verification/CAD Engineers for new graduates. I have completed an MS-Electrical Engineering from USC-Los Angeles.
Skills: verilog, vhdl, c++, hspice, cadence virtuoso, xilinx ise, modelsim, ncsim, synopsys design compiler
Darshan Divecha - Raleigh, ND, USA
Full Time employment
Skills: system verilog, verilog, questasim tool, modelsim, hspice simulation
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